ATV Description

The Algorithmic Test Vector (ATV) system is a low cost, portable, high performance digital tester which represents a major advance and simplification for integrated circuit testing. Its modular architecture and custom ASICs achieve dramatic miniaturization and flexibility while delivering performance found in ATE systems costing many times as much.

ATV Schematic

SIMPLE TEST DEVELOPMENT
With ATV, test development is broken into three separate elements, organized the natural way engineers work with parts:

  • Timing Diagrams
  • Part/Package Description
  • Test Programs

Each of these elements are created and stored separately, then combined at run time. Dynamic combinations allow simple yet powerful test variations. A new part can be tested by merely creating a new package description. Speed enhancements for next generation parts only require new timing diagrams. A single test program can be used for an entire family of parts in various packages. Due to this modularity, dramatically fewer programming elements need to be maintained in your archive. Productivity is enhanced since new tests are assembled using existing pin/package, timing and test program building blocks.

Timing Diagrams - Each ATV pin has independent timing, and can store up to 7 timing sets which are selectable on-the-fly. Timing is specified by graphically creating a set of timing diagrams for each part, similar to the ones found in that parts specification sheets.

ATV formats include NRZ, Return to One, Return to Zero, or Return to Complement. Timing diagrams can be as short as 20nS and edges placed with 180 pS resolution.

 

Timing Wizard - finds pass/fail regions for selected signal.  Plots the region on the timing diagram.  This is a powerful debug and diagnostic tool

Part/Package Description - Interconnections between the tester and DUT are specified graphically. Pins or groups of pins are selected and assigned names from a pull-down list derived from a timing diagram set.

Test Vectors - Test vectors can be imported from ASCII files, or they can be generated real time algorithmically.

Algorithmic generation is powerful because millions of vectors can be generated from a few lines of code. This is especially important when testing memories or devices containing memory blocks.  These vector patterns are generated on-the-fly.  This is ideal for testing complex memories such as FLASH or SDRAM.  As an example for FLASH,  Address, Data and Compare patterns can be multiplexed on the same pins.  For SDRAM interrupts allow for automatic refresh and refresh timing control.

Imported vectors are essential when testing complex devices such as ASICs or microprocessors.

With ATV imported vectors and algorithmic generation can be combined for applications such as SoC, where it might be required to assert import vectors to access embedded memory, then manipulate the memory using algorithmic vector code.

ATV test vector algorithms are programmed in an integrated environment which compiles high level and assembly source code and downloads to the ATV unit. The source language includes subroutines and interrupts. Procedure libraries are also implemented so test algorithms can be simply built by including existing common code.

 

Analog Features- ATV includes a continuity test mode, so interconnections between the DUT and the tester can be confirmed.  The TVP card includes a 1 Amp Vdd supply.  It also includes a built in  SMU for DUT Parametric Measurements. (Voh, Vol, Ioh, Iol, Idd, etc.)  The built in SMU also enables Mixed Signal Testing (ADCs, DACs)

FAST HARDWARE LOOP
ATV provides a hardware feature which repeats a section of text vector code without the time penalty normally associated with software loops. With this feature ATV can algorithmically generate 50 million timing diagrams per second using loop constructs.

EXPANDABLE ARCHITECTURE
ATV uses a synchronized timing architecture and distributed processing so systems can be expanded without limit. A system is comprised of a Test Vector Processor (TVP) card, clock generator, and some mixture of sixteen channel I/O, and twenty four channel Address/Output cards.

TVP Card - The TVP card controls algorithmic program flow for the entire system. It also has a programmable power supply which measures IDDQ currents, 6 output strobe lines, trigger-in and trigger-out controls.

I/O Cards - I/O cards have 16 input and output lines which can be used as I/O pairs or separately.

Address/Output Cards - Address/Output cards have 24 channels.

On I/O or Address cards some or all of the output channels can be assigned to an ax counter which can be initialized, incremented and decremented. The ax counter has an arithmetic logic unit which can generate complex address sequences on-the-fly. Output pins can be multiplexed for testing segmented address devices such as RAS/CAS on DRAMs.

Using ATV, it is not necessary to have the large electronic test heads and associated mechanical manipulators prevalent in many test environments.

Test Head - ATV keeps most of the active electronics in the controller, and connections to the DUT can be as simple as a cable set.  For highest speed and ac testing, the system includes a test head that provides an interface between DUT cards and system cables. The test head has built-in analog buffer drivers for maximum test speeds.

Programmable Thevinin Load - ATV I/O channels have three programmable drive conditions, all of which are asserted on-the-fly as specified in the timing diagrams. Logic high and logic low are used when sending data to the DUT. The third drive condition, reverse terminate, is used to develop a programmable Thevinin load when the DUT is out-putting a signal. A Thevinin load consists of a series resistance back terminated in a voltage source. The reverse terminate drive establishes the voltage source for the load and resistors on the DUT card provide the series resistance.

Error Log - See the expected pattern versus the error pattern.  Double click on the error to see algorithmic step or imported vector where the error occurred.  Failed bits are highlighted on the import test vector file, when importing vectors.

 

Real Time Logical to Physical Map - ATV includes a logical-to-physical mapping tool which displays the logical location of errors or their physical die location.  See the errors in the physical x/y layout.  Scroll through previous test errors.  The address and bit of each error is displayed as the mouse flies over the error.  The logical to physical relations are entered using a built in L2P calculator (reverse polish notation).

AUTOMATED TEST SEQUENCES/PROGRAMS  (ATE)
ATV includes a Visual Basic, Rapid Application Development environment (RAD) for automatic sequencing test algorithms.  From it you can control ATV & PWS and other labe instruments using GPIB, IEE488)  Create operator screens that allow turn key operation of test and ensure data integrity. 

Automated tests can be created quickly using built in Templates.  The smart spread sheet allows you to enter part/Test information in one place.  This information is automatically replicated for all part serial numbers and and test conditions.  It includes binning tables where bin limits for selected parameter are stored.  The smart spread sheet is used in conjunction with a template BASIC program where you add a few procedures for your part and then start testing.  The template program handles all the detail of information management.  It knows where to log data in the smart spread sheet and keeps track of which serial number, step and condition is being tested.  Results are automatically plotted as specified in the smart spread sheet.

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