Frequenty Asked Questions

1) How does support and training work?

JDI provides software and application support by email and phone. The first two months is included in the purchase of the system. This includes free software upgrades as available. Hardware support is by card swap via mail/FedEx. Each system purchase includes a training DVD.  Optionally, training at your facility for an unlimited number of engineers and technicians is available at additional cost. The length of training is typically 4 days. It includes lecture and laboratory "hands on" workshop. We encourage developing an application during training for a DUT the customer wants to test so that the system is immediately in use at the conclusion of training.

Extended service and software support agreements are available in one year intervals.

2) How many I/O channels and Output channels can a digital test system have?

The ATV digital tester has a modular design. The base unit has 16 I/O and 30 output only channels. Pin resources can be added in sets of 16 I/O and 24 Output.  (See Virtual System Builder)

3) What address range can be achieved from the ATV digital tester?

Address ranges are in sets of 24 bits. Addresses longer than 24 bits can be composed by algorithmically combining output cards.

4) Is address de-scrambling possible?

For data coming out of the part, ATV has a powerful logical to physical mapping and translation capability. This includes a logical to physical calculator for defining the de-scrambling equation. Using theses de-scrambling equations, errors are displayed in their true physical location in a visual representation of the die.

For writing data to the part wiring the DUT address bits in the correct sequence combined with some intelligent algorithmic code can achieve true physical mapping.

5) Is Data scrambling possible?

The logical to physical translation equations are written as a function of address and data bits.

6) Are test patterns user-specific programmable or pre-programmed patterns?

The ATV digital tester generates patterns algorithmically as directed by user written algorithms. We have a library of application programs that you can use directly or modify to create algorithms. ATV can also import test vectors from ATPG.

7) How many test vectors deep is the pattern memory in the ATV. Also, does the vector memory have micro-sequencer augmentation (conditional branch, goto, repeat, ...)??

ATV is capable of algorithmic generation of test patterns which means the tester can create patterns on-the-fly based on a user program. This program allows most of the higher language functions you might expect such as loops, branches, variables, conditionals, procedures, etc. The algorithms can be designed so that patterns are generated for the DUT at ATV hardware speeds without interruption. Using algorithms a few lines of code can be used to generate millions of test vector patterns (See example of programming at the end of this message).

Also, ATV can import test vectors. The memory burst depth is 512K. The memory can be refreshed so the effective test vector depth is not limited.

EXAMPLE of ATV programming language (portion of test program for FLASH

      if cmd1 = 0 then
            { **********************************
                  * WRITE/READ ALL ONES PATTERN
loop0:        setcr:= 0X20408; {generate trigger}
                  setcr:= 0X0408;
                  for i := 1 to 1024 do begin
                        loop 64 begin
                              tdg WRITE(OUT(DATA = "1"); OUT(ADDR = ax+));
                              tdg WRITE(OUT(DATA = "1"); OUT(ADDR = ax+))
                         loop 10000 inline(NOP) {wait 10mS for FLASH memory page
                  loop 65536 begin {65536}
                        tdg READ(CMPR(DATA = "1"); OUT(ADDR = ax+));
                        tdg READ(CMPR(DATA = "1"); OUT(ADDR = ax+))

                  if cmd3 = 1 then goto loop0

8) What DUT sockets are available (or easy to change/adapt)?

JDI provides a 4-site general purpose daughter board which mounts on the test head that allows direct wiring of parts and sockets. Also there are commercially available DUT adapter boards that can be used in conjunction with JDI's daughter boards. For instance see

Additionally JDI provides a solderless prototyping daughter board for quick setup and test checkout. For information about our test head and daughter boards see

9) Is it possible to tests SDRAM components and memory modules?

Yes.  JDI provides a library application for performing testing on SDRAM and DDR2 SDRAM. These are available as working projects with application notes, and are included in the price of the purchase of the system at no additional cost.

10) What DRAM/SDRAM refresh modes are available, auto-, self-, "CAS before RAS-refresh?

Yes to All. Your choice since they are implemented algorithmically.

11) Is a mechanically separated DUT socket (via cable) possible?

Yes. The part can be remoted from the tester up to 100 feet. The distance does affect the speed at which the test program can be run. For the SDRAM SEU testing mentioned above the DUT was remoted 20 feet and the test was run at 20MHz.

At some environment sources you may want to leave the test unit within 10 to 20 feet of the DUT and also remote the Monitor, Keyboard and Mouse. This can be accomplished up to 500 feet using a product from

Other customers have used a software product called PCAnywhere to remotely control our units.

12) When running a part at remote distances, what is the influence on minimal cycle time?

ATV automatically corrects for cable delay and can even delay the compare across clock cycle boundaries. The main impact of longer cable length in remote DUT testing is the inherent degradation of rise time in coaxial cable. Therefore with longer cable lengths tests may have to be run more slowly. The distance/test speed degradation is a function of the type of coaxial cable used.

13) Does ATV detect and store errors in real time ("on the fly")?

Errors are detected real time, and stored in FIFOs inside the ATV tester. The errors are transferred to the controlling PC and placed in raw data log. The errors can be transferred at the test conclusion or asynchronously while the ATV tester is running the test.

14) Is a bit-map for fail-bit available (with number of failed bit and fail-bit addresses)?

Yes. This is reported in the data log spread sheet and plotted in the logical to physical view.

15) What is the storage capacity for number of fail-bit and fail-bit addresses?

ATV error FIFO length is 256K, but with asynchronous download the number of errors for failed bits and addresses is essentially unlimited.

16) Can ATV test low voltage differential circuits?

The ATV digital tester does perform testing of low voltage differential circuits. The output pairs from the DUT are connected to separate inputs on ATV. (e.g. requires 2 I/O channels per DUT output) Also the actual DUT differential voltage levels can be measured using PWS.

17) Can PWS test Op Amps and Comparators?

An application note and working project for testing Op Amps and Comparators is included with the system purchase

18) Is this tester good at doing timing characterization of a part? For example, testing a 74act244 during radiation we want to see if the propagation delay through the part slows down. Could you explain how this is done and what the sampling resolution would be? How do you compensate for cable lengths?

You can accomplish this from our test environment in two ways.

a) You can have the ATV digital tester perform an ac test. You would run ATV in SCAN mode where you would specify the output time of the 74act244 to be measured relative to the input. This mode automatically scans ATV's compare timing at the output and reports the timing of the edge. The resolution of the measurement is 180 ps.

ATV is designed to perform remote testing. Its hardware compensates for cable length by internally moving compare edges. This compensation is accomplished independent of test frequency and will even allow compare edges to be slid across clock boundaries so that our tester will work with cable sets that are quite long (~100 feet) ... all transparent to you.

b) Our test environment provides control to other instrumentation via IEEE488 GPIB. In this case you could use ATV to provide digital stimulus and an oscilloscope to make the measurement, then fetch the scope data using GPIB commands into the tester logging environment.

In either case you would use the rich data logging and test control environment of DTE to manage the results.

19) How is calibration achieved? Is there a self-calibration program and is it NBS traceable?

The analog tester has a self calibration program. Calibration consists of taking two external voltage readings when prompted by the auto cal program and all other measurements/calculations are performed automatically. We perform initial factory calibration which is NBS traceable. Calibration constants are stored in a computer file that we provide with the unit. Later calibrations can be performed by you if you have an NBS traceable volt meter.

The digital tester is factory calibrated traceable to NBS for all analog functions. Timing and frequency functions are controlled by a crystal oscillator and phase lock loops.


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